Generally, light emitting diodes (LEDs) for display devices are driven using a constant current to reduce the dispersion of the luminance of the LEDs. When the luminance is adjusted in accordance with the application of the light emitting diode, the current setting of the constant current circuit is changed. However, the voltage drop of the light emitting diode varies depending on the driving current. Because of this feature, the voltage at the output terminal (i.e., the voltage at the output terminal of the constant current circuit) may greatly vary.
Generally, in the constant current circuit, the drain electrode of a MOS transistor is used as the output terminal. However, in this case, there is a problem that when the voltage at the output terminal greatly changes, due to the channel length modulation effect of the MOS transistor, the output current may change and as a result, the luminance of the light emitting diode may change.
To solve the problem, there is a constant current circuit as illustrated in FIG. 9.
In FIG. 9, the NMOS transistors M111, M112, M141, and M142 constitute a low-voltage cascode-type current mirror circuit. Further, the output current iout is supplied to an external load 110 which is connected to an output terminal OUT. The output current iout is obtained by multiplying a current iref by a ratio determined based on the transistor size ratio between the NMOS transistor M111 and the NMOS transistor M112. An error amplification circuit OP102 controls an NMOS transistor M116 so that a voltage of a connection part between a resistor R111 and the NMOS transistor M116 is equal to a reference voltage Vref. In this case, when the resistance value of the resistor R111 is r111, a current iref2 flowing through the resistor R111 is obtained by the formula iref2=Vref/r111. The current iref2 is reflected by PMOS transistors M115 and M114 to become a current iref1, the PMOS transistors M115 and M114 constituting a current mirror circuit.
The NMOS transistors M111, M112, M141, and M142 constituting an output circuit to supply a current to the external load 110 form a cascode-type current mirror circuit. Therefore, the drain voltage of the NMOS transistor M112 becomes equivalent to the drain voltage of the NMOS transistor M111 regardless of the voltage at the output terminal OUT. As a result, the voltage change at the output terminal OUT has a small effect on the output current iout.
However, in a case where an output transistor to supply current to the output terminal OUT is constituted by the NMOS transistors M112 and M142 which are connected in series, even when the output circuit is constituted by the low-voltage cascode-type current mirror circuit, the voltage at the output terminal OUT may be increased. The voltage is necessary for the output transistor to operate in the saturation region where constant current accuracy can be maintained.
For example, when the NMOS transistors M111, M112, M141, M142 are the same conductivity-type transistors and have the same transistor size and the threshold voltage, the gate-source voltage, and the overdrive voltage are denoted by Vthn, Vgs2, and Vov, respectively, the following formula (a) is obtained.Vds1=Vbias−Vgs2  (a)
When the bias voltage Vbias is set to be Vbias=Vgs2+Vov so that the NMOS transistor M112 can operate at the boundary between the linear region and the saturation region, the above formula (a) is changed to the following formula (b).Vds1=Vov  (b)
Similar to the NMOS transistor M112, when the NMOS transistor M142 also operates at the boundary between the linear region and the saturation region, the drain-source voltage Vds2 of the NMOS transistor M142 is expressed by the following formula (c).Vds2=Vov  (c)
Therefore, the minimum voltage Vomin at the output terminal OUT is expressed by the following formula (d).Vomin=Vds1+Vds2=2×Vov  (d)
In a general CMOS process, the minimum voltage Vomin is in a range from 0.6 V to 1.0 V. When the voltage at the output terminal OUT is high, the power consumption consumed by the output transistor of the constant current circuit becomes large. Further, in order to output a large current to drive a light emitting diode, the output transistor having a very large size is required to be used. Because of this feature, when two MOS transistors connected in series are used to constitute the output transistor, the chip area may be greatly increased.
Further, the drain-source voltage of the NMOS transistor M142 greatly varies depending on the voltage at the output terminal OUT. On the other hand, the drain-source voltage of the NMOS transistor M141 becomes equal to a value of (Vthn+Vov)−Vov=Vthn. However, the drain-source voltage of the NMOS transistor M141 differs from the drain-source voltage of the NMOS transistor M142. Namely, the drain-source voltage of the NMOS transistor M111 differs from the drain-source voltage of the NMOS transistor M112. As a result, a systematic error may be generated in the output current iout.
To solve such a problem, as illustrated in FIG. 10, there is the constant current circuit where even when the external load changes, the external load being connected to the output terminal of the constant current circuit, the output current does not change, and even when the voltage at the output terminal is low, the constant current circuit stably operates in the saturation region (see, for example, Patent Document 1).
In this case, when a variable resistor R is appropriately adjusted, the drain-source voltage of the NMOS transistor NT1 is equal to the drain-source voltage of the NMOS transistor NT2 without using the cascade-type current mirror circuit. Therefore, a constant current can be accurately output without generating the systematic error.
However, the drain voltage of the NMOS transistor NT2 can be adjusted only in a range from a voltage where the NMOS transistor NT2 operates in the saturation region to the gate-source voltage of the NMOS transistor NT2. Namely, a range of the voltage Vo at the output terminal OUT where the constant current can output without generating the systematic error is expressed as Vov2≦Vo≦Vthn+Vov2, where Vthn and Vov2 denote the threshold voltage and the overdrive voltage, respectively, of the NMOS transistor NT2. Therefore, there is a problem that a variable range of the voltage Vo at the output terminal OUT may be largely limited.
To resolve such a problem, there is a constant current circuit as illustrated in FIG. 11 (see, for example Patent Document 2).
In FIG. 11, the output terminal voltage range where the accuracy of the output current can be maintained can be expanded by level-shifting and feedbacking the output terminal voltage to the current mirror circuit.
[Patent Document 1] Japanese Laid-Open Patent Application No. 09-319323
[Patent Document 2] Japanese Laid-Open Patent Application No. 2008-227213